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HM621100A Series
1048576-word x 1-bit High Speed CMOS Static RAM
Description
The Hitachi HM621100A is a high speed 1M Static RAM organized as 1048576-word x 1-bit. It realizes high speed access time (20/25/35 ns) and low power consumption, employing CMOS process technology and high speed circuit designing technology. It is most advantageous for the field where high speed and high density memory is required, such as the cache memory for main frame or 32-bit MPU. The HM621100A, packaged in a 400-mil plastic SOJ is available for high density mounting.
Features
* Single 5 V supply and high density 28-pin package (DIP and SOJ) * High speed Access time: 20/25/35 ns (max) * Low power dissipation Active mode: 350 mW (typ) Standby mode: 100 W (typ) * Completely static memory required No clock or timing strobe required * Equal access and cycle time * Directly TTL compatible All inputs and outputs
HM621100A Series
Ordering Information
Type No. HM621100AP-20 HM621100AP-25 HM621100AP-35 HM621100ALP-20 HM621100ALP-25 HM621100ALP-35 HM621100AJP-20 HM621100AJP-25 HM621100AJP-35 Access Time 20 ns 25 ns 35 ns 20 ns 25 ns 35 ns 20 ns 25 ns 35 ns 400-mil 28-pin plastic SOJ (CP-28D) Package 400-mil 28-pin plastic DIP (DP-28C)
HM621100ALJP-20 20 ns HM621100ALJP-25 25 ns HM621100ALJP-35 35 ns
2
HM621100A Series
Pin Arrangement
A0 A1 A2 A3 A4 A5 NC A6 A7 A8 A9 Q WE VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A19 A18 A17 A16 A15 A14 NC A13 A12 A11 A10 D CS
Pin Description
Pin Name A0 - A19 D Q CS WE VCC VSS Function Address Input Output Chip select Write enable Power supply Ground
3
HM621100A Series
Block Diagram
A1 A2 A3 A4 A5 A6 A7 A8 A9 Din Column I/O Dout Column decoder
VCC Row decoder Memory array 512 x 2048 VSS
CS WE
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A0
4
HM621100A Series
Function Table
CS H L L Note: X : H or L WE X H L Mode Not selected Read Write VCC Current I SB , I SB1 I CC I CC Output Pin High-Z Dout High-Z Ref. Cycle -- Read cycle Write cycle
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Power dissipation Operating temperature range Storage temperature range Storage temperature range under bias Note: Symbol Vin PT Topr Tstg Tbias Value -0.5 to +7.0 1.0 0 to +70 -55 to +125 -10 to +85
*1
Unit V W C C C
1. Vin min = -2.0 V for pulse width 10 ns.
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC VSS Input high (logic 1) voltage Input low (logic 0) voltage Note: VIH VIL Min 4.5 0 2.2 -0.5
*1
Typ 5.0 0 -- --
Max 5.5 0 6.0 0.8
Unit V V V V
1. VIL min = -2.0 V for pulse width 10 ns.
5
HM621100A Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
HM621100A-20 Parameter Input leakage current Output leakage current Operating power supply current Standby power supply current Standby power supply current (1) Symbol Min |ILI| |ILO | I CC -- -- -- Typ -- -- --
*1
HM621100A-25/35 Min -- -- -- Typ*1 -- -- -- Max 2.0 2.0 120 Unit Test Conditions A A mA VCC = max Vin = VSS to V CC CS = VIH VI/O = VSS to V CC CS = VIL, II/O = 0 mA, min cycle CS = VIH, min cycle CS V CC -0.2 V 0 V Vin 0.2 V or Vin V CC -0.2 V
Max 2.0 2.0 150
I SB I
*2 SB1
-- --
-- 0.02
60 2.0
-- --
-- 0.02
40 2.0
mA mA
I SB1*3 Output low voltage Output high voltage VOL VOH
-- -- 2.4
-- -- --
100 0.4 --
-- -- 2.4
-- -- --
100 0.4 --
A V V I OL = 8 mA I OH = -4 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. P and JP version 3. LP and LJP version
Capacitance (Ta = 25C, f = 1 MHz)
Parameter Input capacitance Symbol Cin Min -- Max 5 6 Output capacitance Cout --
*2 *3
Unit pF
Test Conditions Vin = 0 V
8
pF
Vout = 0 V
Notes: 1. This parameter is sampled and not 100% tested. 2. SOJ package 3. DIP package
6
HM621100A Series
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.)
Test Conditions * * * * * Input pulse levels: 0 V to 3.0 V Input rise and fall time: 4 ns Input timing reference levels: 1.5 V Output timing reference levels: 1.5 V Output load: See figures
+5V 480 Dout 255 30 pF *1 Dout 255 5 pF *1 +5V 480
Output load (A) Note: 1. Including scope and jig
Output load (B) (For tHZ , tLZ, tWZ and tOW)
Read Cycle
HM621100A-20 Parameter Read cycle time Address access time Chip select access time Chip selection to output in low-Z Chip deselection to output in high-Z Output hold from address change Chip selection to power up time Symbol t RC t AA t ACS t LZ
*1 *1
HM621100A-25 Min 25 -- -- 5 0 5 0 -- Max -- 25 25 -- 12 -- -- 15
HM621100A-35 Min 35 -- -- 5 0 5 0 -- Max -- 35 35 -- 15 -- -- 25 Unit ns ns ns ns ns ns ns ns
Min 20 -- -- 5 0 5 0 --
Max -- 20 20 -- 10 -- -- 12
t HZ
t OH t PU
Chip deselection to power down time t PD Note:
1. Transition is measured 200 mV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested.
7
HM621100A Series
Read Timing Waveform (1) (WE = VIH, CS = VIL )
tRC Address tAA tOH Dout Valid Data tOH
Read Timing Waveform (2)*1 (WE = VIH)
tRC CS tACS tLZ Dout High-Z tPU VCCsupply Current ICC ISB Note: 1. Address valid prior to or coincident with CS transition low. 50% 50% tPD Valid Data High-Z tHZ
8
HM621100A Series
Write Cycle
HM621100A-20 Parameter Write cycle time Chip selection to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Write to output in high-Z Data to write time overlap Data hold from write time Output active from end of write Output hold from address change Symbol Min t WC t CW t AW t AS t WP
*2 *3
HM621100A-25 Min 25 17 20 0 17 0 0 15 0 0 5 Max -- -- -- -- -- -- 15 -- -- -- --
HM621100A-35 Min 35 25 30 0 25 0 0 20 0 0 5 Max -- -- -- -- -- -- 15 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns
Max -- -- -- -- -- -- 12 -- -- -- --
20 15 16 0 15 0 0 12 0
*1
t WR t WZ
*1
t DW t DH t OW t OH
*4
0 5
Notes: 1. Transition is measured 200 mV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested. 2. A write occurs during the overlap of a low CS and a low WE. 3. t WR is measured from the earlier of CS or WE going high to the end of write cycle. 4. Dout is the same phase of write data of this write cycle, if t WR is long enough.
9
HM621100A Series
Write Timing Waveform (1) (WE Controlled)
tWC Address tCW CS tAW tAS WE tDW Din tWZ Dout High-Z Valid Data tOW tOH tDH tWP tWR
10
HM621100A Series
Write Timing Waveform (2) (CS Controlled)
tWC Address tAW tAS CS tWP WE tDW Din High-Z *1 Dout Note: 1. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high impedance state. Valid Data tDH tWR tCW
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
This characteristics is guaranteed only for L-version.
Parameter VCC for data retention Symbol VDR Min 2.0 Typ -- Max -- Unit V Test Conditions CS V CC -0.2 V, Vin V CC -0.2 V or 0 V Vin 0.2 V
Data retention current Chip deselect to data retention time Operation recovery time Note: 1. VCC = 3.0 V
I CCDR t CDR tR
-- 0 5
2 -- --
50*1 -- --
A ns ms
11
HM621100A Series
Low V CC Data Retention Timing Waveform
Data retention mode VCC 4.5 V tCDR tR
2.2 V VDR CS VCC-0.2 V CS 0V
Low Level Input Voltage V IL (Normalized)
1.3 Ta=25C 1.2 1.1 1.0 0.9 0.8 0.7 4.5
4.75
5.0
5.25
5.5
Supply Voltage Vcc (V)
Low Level Input Voltage vs. Supply Voltage
12
HM621100A Series
High Level Input Voltage V IH (Normalized)
1.3 Ta=25C 1.2 1.1 1.0 0.9 0.8 0.7 4.5
4.75
5.0
5.25
5.5
Supply Voltage Vcc (V)
High Level Input Voltage vs. Supply Voltage
1.6 1.4 1.2 1.0 0.8 0.6 0.4
High Level Output Current IOH (Normalized)
Ta=25C Vcc=5V
1
2
3
4
5
High Level Output Voltage VOH (V)
High Level Output Current vs. High Level Output Voltage
13
HM621100A Series
Low Level Output Current I OL (Normalized)
1.6 1.4 1.2 1.0 0.8 0.6 0.4
Ta=25C Vcc=5V
0
0.2
0.4
0.6
0.8
Low Level Output Voltage VOL (V)
Low Level Output Current vs. Low Level Output Voltage
10 -4 Vcc=3V CS=2.8V 10 -5
Standby Current ISB1 (A)
10 -6
10 -7 0
20
40
60
80
Ambient Temperature Ta (C)
Standby Current vs. Ambient Temperature
14
HM621100A Series
1.4
Standby Current ISB1 (Normalized)
1.2 1.0 0.8 0.6 0.4 0.2
Ta=25C CS=Vcc-0.2V
2
3
4
5
6
Supply Voltage Vcc (V)
Standby Current vs. Supply Voltage
1.6 Ta=25C 1.4
Supply Current Icc (Normalized)
1.2 1.0 0.8 0.6 0.4 4.5
4.75
5.0
5.25
5.5
Supply Voltage Vcc (V)
Supply Current vs. Supply Voltage
15
HM621100A Series
1.6 Vcc=5.0V 1.4
Supply Current Icc (Normalized)
1.2 1.0 0.8 0.6 0.4
0
20
40
60
80
Ambient Temperature Ta (C)
Supply Current vs. Ambient Temperature
1.3 Ta=25C
Access Time t AA ,t ACS (Normalized)
1.2 1.1 1.0 0.9 0.8 0.7 4.5
4.75
5.0
5.25
5.5
Supply Voltage Vcc (V)
Access Time vs. Supply Voltage
16
HM621100A Series
1.8
Access Time t AA ,tACS (Normalized)
1.6 1.4 1.2 1.0 0.8 0.6
0
50
100
150
200
Load Capacitance C L (pF)
Access Time vs. Load Capacitance
1.3
Access Time tAA ,tACS (Normalized)
Vcc=5.0V 1.2 1.1 1.0 0.9 0.8 0.7
0
20
40
60
80
Ambient Temperature Ta (C)
Access Time vs. Ambient Temperature
17
HM621100A Series
1.4 1.2 1.0 0.8 0.6 0.4 0.2 100 50 33 25 T (ns) 20
Supply Current Icc (Normalized)
0
10
20
30
40
50
Frequency f (MHz)
Supply Current vs. Frequency
18
HM621100A Series
Package Dimensions
HM621100AP/ALP Series (DP-28C)
34.70 35.56 Max Unit: mm
28
15 9.64 9.91 Max
1 0.89
1.27 Max
1.30
14 5.08 Max 10.16
0.51 Min
2.54 Min
2.54 0.25
0.48 0.10
0.25 - 0.05 0 - 15
+ 0.11
HM621100AJP/ALJP Series (CP-28D)
18.17 18.54 Max 28 15 10.16 0.13 11.18 0.13
Unit: mm
1 0.74
14
3.50 0.26
0.21 2.40 + 0.24 -
1.30 Max
0.43 0.10
1.27 0.10
0.80
+0.25 -0.17
9.40 0.25
19

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